Senior CPU Design Engineer- FE Integration and FE Flow

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The person will lead sophisticated front-end integration projects and quality assurance initiatives across BDC, IDC, and US teams.
This senior role involves driving complex subIP integration activities, providing expert-level static methodology sign-off, and ensuring comprehensive design quality through advanced analysis techniques.
Will lead complex subIP integration activities and serve as an expert in static methodology sign-off processes.
This senior role requires deep expertise in front-end integration methodologies, advanced static analysis techniques, and comprehensive quality assurance practices.
The candidate will drive end-to-end integration workflows, mentor junior team members, and ensure design quality through expert-level application of CDC, RDC, Lint, and low-power static sign-off methodologies.
This position demands strong technical leadership, cross-functional collaboration skills, and the ability to resolve complex integration challenges across multiple Intel development sites.

The ideal candidate should have experience in many or all the following • Minimum of 7 years of work experience, Should have experience in end-to-end subIP integration activities for complex CPU designs across multiple sites • Provide expert-level static sign-off including CDC, RDC, Lint, and VC-LP methodologies • Drive quality assurance processes and establish design quality metrics and standards along with developing and optimize integration flows and methodologies for improved efficiency. • Mentor team members and engineers and provide technical guidance on integration best practices • Collaborate with teams to ensure seamless integration.
Resolve complex integration challenges and debug sophisticated design issues. • Lead cross-site technical discussions and drive consensus on integration approaches.
Interface with vendor partners to resolve advanced tool issues and drive enhancements. • Establish and maintain integration guidelines, standards, and best practices.
Drive continuous improvement initiatives for integration processes and quality metrics Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

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