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About This Role
- Intel is shaping the future of technology to help create a better future for the entire world.
- Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations.
- With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life.
- Join us and help make the future more wonderful for everyone.
- Want to learn more? Visit our YouTube Channel or the link below.
- Life at Intel Position Summary: The Semiconductor Packaging Research Engineer drives technology research for advanced packaging and heterogeneous integration .
- The role is suited for candidates with expertise in either packaging process integration or modeling / simulation , with a focus on evaluating new architectures, materials, interconnects, reliability risks, and manufacturability trade-offs for future products .
- Key Responsibilities Research advanced packaging concepts such as chiplets, heterogeneous integration, 2.5D/3DIC, hybrid bonding, interposer , and die-to-die interconnects.
- Drive either process integration learning or modeling/simulation to assess feasibility, reliability, manufacturability, and technology readiness.
- For process integration: define integration flows, research vehicles, DOE, defect/yield learning, qualification evidence, and risk mitigation paths.
- For modeling: develop and validate thermal, thermo-mechanical, electrical, reliability, or multi-physics models using experimental and failure analysis data.
- Translate product needs into research hypotheses, technical plans, and recommendations; document outputs through reports, design guidance, IP, publications, and development-transfer inputs.
- Collaborate across research, design, process, materials, reliability, manufacturing, supplier, university, and ecosystem teams.
- For information on Intel’s immigration sponsorship guidelines, please see Intel U.S.
- Immigration Sponsorship Information Qualifications: Minimum qualifications are required to be initially considered for this position.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Required Qualifications Master’s or Ph.D. in Mechanical Engineering, Electrical Engineering, Materials Science, Applied Physics, Computational Mechanics, Microelectronics, Semiconductor Manufacturing, or related field . 1+ years ’ e xperience in semiconductor packaging research, advanced packaging integration, process integration, modeling/simulation, reliability, materials, or heterogeneous integration. 1+ years' experience in one or more of the following area s : process integration, research vehicle execution, DOE, defect/yield learning, reliability, model development & validation , or multi-physics simulation. 1+ year s ' experience with advanced packaging technologies such as flip chip , chiplets, 2.5D/3DIC, fan-out, hybrid bonding, interposers, HBM integration, advanced substrates, or die-to-die interconnects. Preferred Qualifications Ph.D. or deep technical specialization in packaging process integration, computational mechanics, thermal sciences, electrical modeling, materials reliability, or microelectronics research and 4+ years of relevant experience.
- Experience with prototype builds, technology readiness assessment, research-to-development transfer, package-system co-optimization, or chip-package-board co-design.
- Modeling tool experience such as ANSYS, Abaqus, COMSOL, HFSS, Cadence, MATLAB, Python, JMP, or equivalent platforms.
- Record of patents, publications, conference presentations, technical reports, methodology development, or competitive technology assessments.
- Ability to turn ambiguous research problems into clear assumptions, experiments, learning milestones, qualification metrics, and actionable recommendations.
- Key Competencies Advanced packaging research and pathfinding Process integration or modeling/simulation expertise Heterogeneous integration, chiplet, and advanced substrate knowledge DOE, prototype learning, reliability assessment, or model validation Technology readiness evaluation and cross-functional communication Success Measures Research outputs identify credible integration options, technology limiters, and trade-offs for future platforms.
- Process integration or modeling results are supported by clear assumptions, evidence, validation data, and documented limitations.
- Prototype, DOE, or simulation learning improves feasibility, reliability, integration robustness, and manufacturability understanding.
- Key risks are identified early with practical mitigation paths and development-transfer recommendations.
- Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
- Benefits at Intel Our total rewards package goes above and beyond just a paycheck.
- Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals.
- Go to Intel Benefits | Intel Careers for details of benefits available to you.
- Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
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Open roles at Intel
590 positions
Job ID
/job/US-Arizona-Phoenix/Semiconductor-Packaging-Research-Engineer_JR0286871
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