Reliability Verification Technical Manager

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About This Role

  • As a PDK Engineering Manager, you will play a pivotal role in driving Intel's technological innovation and ensuring the development of high-quality process design kits (PDKs).
  • You will lead a team of talented engineers responsible for crafting, validating, and optimizing PDK collateral to support design teams across Intel's product lines.
  • Your role will have a direct impact on enabling cutting-edge designs, fostering collaboration between manufacturing process engineering and design teams, and ensuring seamless methodologies for Intel's advanced process nodes.
  • By developing productive environments, driving solutions, and inspiring your team, you will contribute to Intel's success in delivering world-changing technology that enriches lives globally.
  • Key Responsibilities: - Lead, develop, and manage a team of PDK and design methodology engineers to deliver robust PDK collateral for internal and external design communities for ASIC EM/IR, ESD PERC and High Voltage domain check methodologies . - Oversee quality assurance activities, ensuring validation issues are logged in a ticketing database, tracked, and resolved prior to release. - Drive innovation in tools, flows, and methods to optimize design functions such as circuit design, physical design, and verification. - Collaborate with manufacturing process engineering and design teams to align methodologies with process technology requirements. - Conduct root cause analyses for PDK/TFM issues related to PDK Collaterals, Tool and Flow methodologies and implement corrective actions to close gaps. - Bridge gaps between cross-functional teams and foster efficient, cost-effective operations by developing robust build, run, and flow management environments. - Foster a productive work environment by setting clear goals, maintaining accountability, and supporting differentiated performance management. - Role model Intel values, inspire the team, and focus on developing capabilities to drive exceptional results.

Requirements

  • Bachelor's degree in Electronics, Computer Science, or a related field. - 10+ years of industry experience with a Bachelor's degree, 8+ years with a Master's degree, or 5+ years with a PhD. - Technical expertise in ASIC EM and IR Flow methodologies us Synopsys RHSC/Cadence Voltus - Experience in PDK development and quality assurance. - Experience in ESD PERC flow methodologies using ICV/Calibre or Pegasus - Proficiency in EDA tools from multiple vendors, as well as PDK contents including variation and aging. - Strong skills in planning, prioritization, and delegation to manage a high-functioning team. - 2+ year experience in managing a team.

Nice to Have

  • Good Experience with ASIC EM and IR flow methodologies using Synopsys RHSC and Cadence Voltus ; Experience in technology file developments and and Tool certification process. - Experience in ESD PERC flow methodologies and ESD PERC runset development. - Proven ability to build and evolve organizational capabilities. - Exposure to advanced IC manufacturing process nodes and standard engineering practices such as reliability, variation, and low-power design. - Effective communication skills for engaging across organizational levels, customers, and suppliers. - Motivation to continuously improve organizational processes and enhance team offerings.
  • We value your expertise and innovative mindset.
  • Join us to lead, inspire, and drive Intel's mission to create transformative technology for a better tomorrow.

Tools & Skills

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Intel

India, Bangalore

Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
Open roles at Intel
68 positions
Job ID
/job/India-Bangalore/Reliability-Verification-Technical-Manager_JR0282028

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