Principal Analog Circuit Design Engineer - SerDes

Requirements

• Master's degree in Electrical Engineering, Electronics Engineering, or related field. • 8+ years of experience in analog/mixed-signal circuit design for high-speed SerDes applications. • Proven expertise in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, or Transmitter (TX) design. • Strong understanding of high-speed communication standards such as PCIe (Gen5/Gen6) and Ethernet (100G/400G/800G). • Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity. • Hands-on experience with advanced FinFET CMOS process technologies (7nm or below). • Proficiency in analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent. • Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits. • Excellent communication, documentation, and presentation skills. • Strong problem-solving attitude and ability to deliver under tight schedules in a collaborative environment.
• Preferred Qualifications • Ph.D. in Electrical Engineering, Electronics Engineering, or related field. • 10+ years of experience in analog design for high-speed SerDes (56G/112G/224G) applications. • Deep expertise in transmitter and receiver architecture, CDR loops, equalization techniques, and advanced ADC architectures. • Familiarity with next-generation standards such as PCIe 6.0+, 800G/1.6T Ethernet, JESD, and other SerDes protocols. • Hands-on experience in behavioral modeling (Verilog-A), MATLAB-based analysis, and automation scripting (Python/Tcl/Perl). • Strong understanding of signal integrity, channel modeling, and system-level link performance. • Proven ability to mentor junior engineers, guide layout implementation, and drive design reviews. • Demonstrated leadership in cross-functional technical discussions and decision-making. • Team player with a collaborative mindset, willingness to share knowledge, and a hands-on approach to problem-solving.