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About This Role
- About Intel's Central Engineering Group Intel's Central Engineering Group (CEG) focuses on enhancing engineering execution and expanding market opportunities through internal product development and external ASIC design services.
- Guided by a data-driven approach, CEG drives scalable, impactful solutions across Intel's engineering processes while maintaining a commitment to delivering high-quality results.
- Join a team dedicated to revolutionizing engineering methodologies and supporting Intel's industry leadership.
- Position Overview As an IP Design Verification Engineer, you will play a crucial role in ensuring the functional accuracy and reliability of clock generator IPs, such as PLL and FLL, within Intel's innovative product development lifecycle.
- You will actively develop verification environments, implement tests, and debug pre-silicon issues to meet rigorous specification requirements.
- Your contributions will directly impact the seamless integration of IPs into Intel's cutting-edge designs and ensure the highest standards of quality and performance.
- Key Responsibilities Develop test benches, verification environments, and tests using SystemVerilog and UVM to ensure comprehensive IP validation Perform functional verification for clock generator IPs such as PLL and FLL, ensuring conformance to microarchitecture specifications Maintain and refine verification infrastructure and methodologies for multiple IP generations Debug and root-cause pre-silicon issues within the verification environment Document test plans and participate in technical reviews with design teams Collaborate cross-functionally with architects, RTL developers, and analog design teams to enhance verification of architectural and microarchitectural features Lead Mixed Signal Validation activities, including AMS simulations, schematic debugging, and resolving cross-functional issues Contribute to the definition and refinement of architectural and microarchitectural features for IP design What We're Looking For To be successful in this role, you should demonstrate the following professional traits: A collaborative mindset with the ability to work effectively across cross-functional teams including architects, RTL developers, and analog design teams Strong attention to detail when documenting test plans, debugging pre-silicon issues, and ensuring conformance to specification requirements A proactive approach to problem-solving, with the ability to root-cause complex technical issues and drive them to resolution Qualifications: Minimum Qualifications Bachelor's Degree in Electrical or Computer Engineering or a related field, with 4+ years of relevant experience; OR Master's Degree in Electrical or Computer Engineering or a related field, with 3+ years of relevant experience; OR PhD in Electrical or Computer Engineering or a related field, with 1+ years of relevant experience 2+ years of experience in/with: Design verification and validation methodologies, including UVM, SystemVerilog, and industry-standard EDA tools Scripting languages such as Python and Perl Preferred Qualifications Expertise in SystemVerilog UVM coding and debugging Familiarity with PLL/FLL or SOC clocking and related RTL development Join Intel's Central Engineering Group today, where your skills will drive innovation, quality, and engineering excellence while advancing Intel's industry-leading technology solutions.
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $122,440.00-172,860.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
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Salary range
₹5-12 LPA to ₹40-70 LPA
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Job ID
/job/US-Oregon-Hillsboro/Pre-Silicon-Verification-Engineer_JR0287850
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