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About This Role
- As a Physical Design Timing Engineer, you will play a pivotal role in shaping the performance and efficiency of cutting-edge DDRPHY IP design.
- Your expertise in timing analysis, optimization, and clock network design will directly contribute to delivering high-performance, low-power solutions that drive Intel's innovative products forward.
- Working at the intersection of architecture, logic design, and physical design, you will have the unique opportunity to influence methodologies, ensure design robustness, and optimize power and performance, making a meaningful impact on Intel's industry-leading technologies.
- Key Responsibilities: Perform chip/block-level timing analysis and optimization for IP, identifying and resolving violations to ensure functionality and performance targets are met.
- Generate and verify timing constraints, conducting timing rollups for efficient physical design processes.
- Design and optimize power and performance-efficient clock networks, ensuring adherence to product requirements.
- Develop and refine methodologies for high-quality timing models to streamline physical design workflows.
- Define process, voltage, and temperature (PVT) conditions for timing analysis based on operating conditions and product binning plans.
- Collaborate with architecture, clock design, and logic design teams to develop integration workflows and validate clock network guidelines.
- Work closely with backend design teams for clock balance, timing corrections, power delivery, and partitioning strategies.
- Conduct noise glitch and signal integrity analysis, ensuring design robustness under diverse conditions.
- Contribute to tools, flows, and methodology (TFM) development to support efficient implementation and optimization processes.
Requirements
- to be initially considered for this position.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Requirements
- Bachelor's degree with 6+ years of experience, or Master's degree with 4+ years of experience, or PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or a related field in physical design timing engineering or SoC development. 2+ years of experience with the following skills: Proficiency in static timing analysis tools and methodologies.
- Expertise in clock design, timing budgeting, and constraint adaptation.
- Hands-on experience with TCL scripting for flow development and optimization.
- Strong technical knowledge of physical design fundamentals, including extraction, noise glitch analysis, and signal integrity.
- Familiarity with FEM/PV scaling methods and library characterization.
Nice to Have
- Previous experience in memory design, collaborating across architecture, design, and physical implementation teams.
- Demonstrated problem-solving skills and ability to address complex timing challenges under tight deadlines.
- Effective communication and teamwork abilities to contribute in a cross-functional environment.
- Experience in developing tools, methodologies, or workflows that enhance physical design efficiency.
- We invite you to be part of Intel's journey to deliver transformative technologies.
- Apply today to contribute to pioneering advancements in semiconductor design and innovation.
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Sourced directly from Intel’s career page
Your application goes straight to Intel.
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Salary range
₹5-11 LPA to ₹38-65 LPA
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Job ID
/job/US-Arizona-Phoenix/Physical-Design-Timing-Engineer_JR0283414
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