PDK Engineer

About This Role

• We are looking for a skilled DRC Runset Engineer to develop, validate, support, and optimize Design Rule Checking runsets for advanced semiconductor process technology nodes.
• The candidate will work closely with process development teams, design rule owners, CAD/EDA teams, and design groups to translate design rules into robust, efficient, and production-quality rule decks.
• The role requires strong expertise in DRC rule deck development using industry-standard physical verification tools such as Siemens Calibre, Synopsys ICV, and Cadence Pegasus, along with strong debugging, automation, and problem-solving skills.
• Key Responsibilities: • Develop, maintain, and support DRC runsets/rule decks for advanced semiconductor process nodes. • Translate process design rules into accurate and efficient physical verification checks. • Develop and validate complex geometric, connectivity, density, and process-specific design rule checks using tools such as Calibre, ICV, and Pegasus. • Create comprehensive test cases to validate rule deck functionality, coverage, and correctness. • Debug DRC rule deck issues and resolve customer/user-reported problems. • Improve runset quality, runtime efficiency, scalability, and usability. • Work closely with process developers, design rule owners and develop runsets. • Design and implement unit-level and end-to-end validation methodologies for DRC runsets and physical verification flows. • Provide solutions for complex physical verification and design rule implementation challenges. • Use AI-based tools and automation techniques to improve rule deck development, validation, and debug productivity. • Support production users and resolve runset-related issues in a timely manner. • Work in a fast-paced, dynamic environment with strong ownership, creativity, and attention to quality.