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About This Role
- The Role and Impact: Join our team as a Mixed Signal Logic Design Engineer, where you will play a pivotal role in developing cutting-edge mixed signal and high-speed IP solutions.
- Your expertise will drive the creation of critical design blocks, enabling seamless integration into complex SoC designs.
- By leveraging your skills in logic design, RTL coding, simulation, and architecture definition, you will ensure optimal power, performance, area, and timing goals, as well as design integrity.
- This position empowers you to push boundaries in innovation and contribute directly to Intel's success in delivering world-class products to the market.
- Key Responsibilities: - Develop logic design and RTL coding for mixed signal subsystems and high-speed IP blocks, adhering to performance and quality standards. - Collaborate with SoC architects and analog teams to define interfaces, ensuring proper synchronization and integration of analog and digital domains. - Optimize low-power designs using advanced techniques such as power gating and clock gating, ensuring alignment with area, timing, and power requirements. - Conduct static timing analysis (STA) and resolve timing exceptions to meet design closure objectives. - Review verification plans and debug RTL tests to ensure design features are verified accurately and efficiently. - Provide technical documentation for design processes and support SoC customers to enable high-quality integration of IP blocks.
Requirements
- Candidate should possess 10+ year of experience with at least a master's degree in electrical engineering or equivalent - Proficiency in RTL coding with Verilog/SystemVerilog, technical documentation, and digital design fundamentals. - Hands-on expertise in low-power design techniques such as UPF coding and debug, clock gating, and power gating. - Deep knowledge of static timing analysis (STA) and clock domain crossing (CDC) strategies. - Experience with EDA tools, including lint tools and timing exception management. - Experience with DDR/LPDDR/UCIe interfaces and advanced technology nodes.
Nice to Have
- Advanced knowledge of mixed signal simulation methodologies and formal verification tools. - Demonstrated leadership in task force management or technical mentoring. - Strong analytical and problem-solving abilities, with experience working collaboratively across cross-functional teams. - Exposure to post-silicon debug techniques or interface IPs such as HBM and LPDDR.
- Join us to shape the future of technology, work with world-class teams, and elevate your career to new heights.
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Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
Open roles at Intel
98 positions
Job ID
/job/India-Bangalore/Mixed-Signal-Logic-Design-Engineer_JR0283660
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