Mixed Signal Design Verification Engineer

Requirements

• Candidate must possess Bachelor's or Master's degree in Electronics, VLSI Engineering, or a related field with 4-10 years of relevant industry experience and good proficiency in verification of mixed signal IP Design. • Candidate must be experienced in validation flow right from testbench architecture and test plan creation to verification closure, waveform debugs, functional coverage, code coverage, VCS NLP and non-NLP simulations and GLS. • Strong knowledge of SystemVerilog and UVM methodology, experience in functional and coverage driven verification. • Expertise in constraint-random test generation, failure root cause analysis and debugging of complex mixed signal designs. • Capable of multitasking in dynamic environment with multiple teams from different geos. • Solid verbal and written communication skills. • Excellent debug and problem solving skills.
• Preferred Qualifications • Knowledge of UCIe PHY validation or any high speed PHY IO Mixed Signal IP validation. • Knowledge of Formal Property Verification tools, exposure to emulation. • Good scripting skills in Python/Perl. • Exposed to Git version control. • VS Code GitHub CoPilot or any other AI experience.