Memory Layout Manager

About This Role

• The Role and Impact We are seeking a skilled and motivated Layout Design Engineering Manager to lead a team of layout engineers in delivering best in class SRAM,RF,ROM,CAM Memory compiler designs across the Intel's bleeding FinFETs,GAA technologies.
• In this role, you will champion technical execution by overseeing compiler friendly and optimized floorplanning, high-density,performance based placement and routing template, and rigorous physical sign-off processes including DRC, LVS, Yield, DFM, Density, parasitic extraction, Noise Reliability i.e.
• You will provide technical guidance, set clear goals, and foster cross-functional collaboration with circuit design, Tilers, and foundry teams to meticulously optimize memory area, performance, power, and yield.
• Beyond daily execution, you will spearhead layout methodology innovations, establish advanced automation flows using SKILL, Python, or Tcl, and cultivate a culture of technical excellence by mentoring senior and staff-level engineers.
• The role requires a strong vision for leveraging AI and ML technologies (such as reinforcement learning for routing or predictive analytics for DRC debugging) to make execution significantly more efficient, robust, and high-quality.
• Business group The Intel Foundry group plays a pivotal role in enabling innovative semiconductor manufacturing solutions that power Intel's products and those of our partners worldwide.
• As part of the BA Memories organization, this position supports the development of advanced memory technologies and methodologies, empowering Intel's mission to shape the future of technology and create world-changing advancements.
• Key Responsibilities - Lead and mentor a team of layout design engineers to developed world class memory compiler designs on FinFets/GAA technologies, ensuring alignment with organizational goals and timelines. - Oversee the design, development, modification, analysis, and verification of memory compiler layout designs. - Provide technical guidance for analog, digital, memory, and standard cell layout methodologies, compilers, tools, and flows. - Enable teams to execute effectively by setting clear objectives, maintaining accountability and facilitating productive workflows through AI-driven EDA tools and generative machine learning models into the design lifecycle to automate repetitive layout tasks, accelerate routing, and optimize cell placement. - Drive team results by inspiring and developing team members, modeling Intel values, and fostering a supportive and collaborative environment. - Manage resources effectively to optimize project execution and meet performance targets.