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About This Role
- Responsibilities will include but are not limited to: Develop and drive analog and mixed-signal IP architectures, signal processing algorithms, and calibration algorithms for system-on-chip (SoC) independent AMS IPs.
- Conduct top-down architectural analysis of AMS systems and perform transistor-level feasibility studies for various AMS circuits.
- Design novel architectures and define microarchitectures for next-generation AMS IP to achieve optimal performance, power, and area for diverse product segments.
- Enhance system performance by leveraging digitally assisted analog techniques and optimizing the partitioning of analog and digital circuits.
- Evaluate trade-offs, explore innovative approaches, and provide proof-of-concept design alternatives for AMS systems.
- Collaborate with IP design and verification teams to define, develop, and validate robust AMS IPs for SoC integration.
- Support SoC architects, design engineers, and verification engineers in selecting, configuring, and validating SoCs that leverage AMS IPs.
- Perform modeling, simulation, and optimization for power, area, and performance metrics, analyzing test results to identify improvement opportunities.
- Define future AMS IP technology targets by influencing cross-functional roadmaps and reviewing emerging technology trends.
- The ideal candidate should show the following behavioral traits: Strong communication and collaboration skills, with the willing to mentor and technically guide team members.
Requirements
- are required to be initially considered for this position.
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related STEM field with 9+ years of experience.
- OR Master's degree in in Electrical Engineering, Computer Engineering, or related STEM field with 6+ years of experience.
- OR PhD in Electrical Engineering, Computer Engineering, or related STEM field with 3+ years of experience.
- Experience listed above should be a combination of the following: Analog and mixed-signal circuit design within standard CMOS technologies, including op-amps, comparators, bandgap references, and linear regulators.
- Backend verification tools such as Monte Carlo simulations, EMIR, and static/dynamic MOSFET voltage checks.
- Analog behavior modeling and system-level understanding of AMS circuits.
- Hands-on experience with transmission line theory and AMS system modeling.
- Architectural feature definition, high-speed design techniques, and IP architecture definition.
- Proven experience with high speed PHY designs from concept through qualification.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Proficiency in MATLAB or similar tool base modeling.
- Experience in post-silicon debugging and high-volume productization of designs.
- Familiarity with signal integrity and power integrity analysis.
- Background in analog layout techniques, including floor-planning, matching, shielding, and parasitic optimization.
- Join us and work alongside some of the brightest minds in the industry.
- Together, let us change the future of technology and do something truly wonderful.
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
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Specialisation
Open roles at Intel
666 positions
Job ID
/job/US-California-Santa-Clara/High-speed-PHY-System-Architect_JR0284922
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