Electromagnetic Modeling Student Worker

About This Role

• This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position.
• The IOTS Pathfinding team is seeking a motivated and detail-oriented Engineer Intern to join our team in Guadalajara.
• In this role, you will support readiness and scalability for next-generation high-speed I/O technologies (PCI Express, UPI, CXL, USB) by assisting in technology pathfinding projects critical to future server platforms and Intel's data center leadership.
• You will develop and validate high-fidelity 3D electromagnetic (EM) model libraries for key interconnects-such as connectors, PCB vias, and high-speed cables-using industry-standard tools (e.g., Ansys HFSS, CST, ADS) to support signal integrity (SI) and power integrity (PI) evaluations.
• You will collaborate with engineers across Intel's I/O community and, as needed, interact with external industry organizations.
• Under mentorship, you will help execute parametric studies and optimization sweeps to explore SI/PI performance and manufacturability tradeoffs, assist with correlating simulations to lab/bench measurements, and contribute to documentation such as a best-practices / design-guidelines report and reusable modeling workflows for design teams.
• Key Responsibilities Assist in building, parameterizing, and organizing 3D EM models for connectors, PCB via structures, and high-speed cable/interconnect assemblies using tools such as Ansys HFSS, CST Microwave Studio, and/or ADS.
• Run defined parametric studies (geometry, materials, plating/roughness, stack-up, launch transitions) to quantify impact on SI/PI metrics (e.g., insertion/return loss, impedance, mode conversion, crosstalk, resonance behavior) and summarize results.
• Support model validation and correlation by helping compare EM results to lab/bench data (e.g., VNA measurements, TDR, fixture de-embedding) and documenting model assumptions, accuracy, and limitations.
• Assist with analysis of simulation results to identify trends and potential optimization opportunities, and help capture design tradeoffs (performance, cost, manufacturability) for connector/via/cable implementations.
• Help create and maintain deliverables including model files/libraries, solver setups, scripts for parameter sweeps and post-processing, and clear documentation to enable reuse by design teams.
• Contribute to a best-practices report and modeling/optimization guidelines for EM extraction workflows supporting SI/PI assessment of connectors, vias, and high-speed cables (e.g., recommended steps, settings, and checklists).
• Present progress and findings in team meetings; collaborate with SI/PI, package/board design, and validation engineers to incorporate feedback and improve the model library and documentation.
• Behavioral Traits Eagerness to learn and apply new technical concepts.
• Sense of ownership and accountability for assigned tasks.
• Work effectively in a team-oriented environment.
• Proactive, organized, and able to manage multiple tasks.
• Open to feedback and continuous improvement.
• What You Will Learn Experience with 3D electromagnetic (EM) simulation for interconnects using industry tools such as Ansys HFSS, CST Microwave Studio, and/or ADS.
• Skills on signal integrity (SI) and power integrity (PI) behavior of connectors, PCB vias, and high-speed cables using frequency/time-domain metrics (e.g., S-parameters, TDR, crosstalk).
• Skills in workflow automation for parametric sweeps and post-processing (e.g., scripting, data reduction, plotting) to turn simulation runs into actionable insights.
• Exposure to model validation and correlation methods, including comparing simulations to lab/bench measurements (e.g., VNA, TDR) and understanding fixture effects and de-embedding concepts.
• Experience in creating reusable model libraries and best-practices guidelines, and how to communicate technical results effectively across SI/PI, board design, and validation teams.