E-core CPU Full Chip Physical Design Engineer

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About This Role

  • Become a key member of a team participating in the physical design construction and integration and verification of a future Intel CPU.
  • This position requires an engineer with broad physical design and STA skills, coupled with leadership skills necessary to drive methodology and to collaborate effectively with multiple functional teams within the CPU design team.
  • We are looking for a talented individual to drive the physical convergence of a Full-Chip (FC) assembly of partitions.
  • As a Full Chip design engineer, you will perform floorplanning, pin and feedthrough planning, repeater insertion, power grid generation and assembly of partitions.
  • Given the need for executing multiple projects in parallel, you will be responsible for driving efficiency and quality improvements to the overall FC methodology - including floorplan optimization for better utilization/QoR/runtime and timing and physical aware feedthrough/pin placement.
  • You will also be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR.
  • You will drive physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis).
  • The ideal candidate should have an aptitude to work effectively with EDA tools and exhibit behavioral traits that indicate: Ability to work well in a team and be productive under aggressive schedules Excellent written and verbal communications skills Self-motivation and well organized Qualifications: You must possess the below minimum qualifications to be initially considered for this position.
  • Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Requirements

  • Must have either BS or MS in Electrical Engineering or Computer Engineering Minimum 7 years of experience in CPU physical design and timing verification Synthesis/APR flows on multi voltage high frequency designs including custom polygon editing Tcl scripting Noise, cross-talk, OCV analysis.
  • Floorplanning and physical design and timing closure.

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Intel

Malaysia, Penang

Specialisation
Salary range
₹5-11 LPA to ₹38-65 LPA
Open roles at Intel
732 positions
Job ID
/job/Malaysia-Penang/E-core-CPU-Full-Chip-Physical-Design-Engineer_JR0288281

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