DFT RTL Design and Integration Engineer

About This Role

• Develop the logic design, Register Transfer Level (RTL) coding, simulation, and provide DFT timing closure support.
• Define and Implement SoC main debug Fabrics - TAP and Scan.
• Develop automatic tools to expedite and improve design and integration.
• Closely work with Architecture and uArch, Silicon and Manufacturing teams to define new features and improve DFT capabilities - Power, Performance, Test Time, coverage and more.
• Define validation activities and work with validation owners to increase coverage and design quality.
• Define IPs DFT requirements to meet SoC needed quality, support IPs integration and validation.
• Develop HVM ready content, enable it on Pre Si ENV as well as on real Silicon.
• Dirve Coverage improvement, DPM reduction and faster Content enabling on Silicon.