DFT Design Engineer

About This Role

• Design, implement, validate, and debug Design-for-Test (DFT) solutions to ensure manufacturability, test coverage, and silicon quality across IP and SoC programs.
• Responsibilities include development and validation of TAP/JTAG and IJTAG infrastructures, Boundary Scan (BSCAN), MBIST, Scan/ATPG methodologies, and associated test collateral such as ICL, PDL, BSDL, and ATPG patterns.
• The role requires driving test access, pattern generation, coverage optimization, memory test validation, and debug of scan, at-speed, and silicon bring-up issues while ensuring robust DFT integration across the product lifecycle.
• The engineer collaborates closely with Design, Verification, Physical Design, Product Engineering, Manufacturing Test, and IP teams to ensure DFT readiness and signoff.
• Key responsibilities include RTL and Gate-Level Simulation (GLS) validation, root-cause analysis and resolution of DFT-related failures, adoption of DFT methodologies and best practices, and leadership of technical reviews and continuous process improvements.
• Required expertise includes TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, Scan Compression, ATPG, Verilog/SystemVerilog, Tcl/Perl/Python scripting, DFT verification, silicon debug, and strong communication and technical leadership skills.