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About This Role
- A Design Verification (DV) Intern supports pre-silicon validation by developing testbenches, running simulations, and debugging digital ICs.
- They collaborate closely with RTL designers to ensure functional correctness and achieve verification closure, gaining hands-on exposure to industry-standard methodologies.
- Key Responsibilities Testbench Development: Assist in developing and enhancing constrained-random verification components (e.g., sequences, monitors, scoreboards) using SystemVerilog and UVM (Universal Verification Methodology).
- Simulation & Debugging: Execute regression tests, analyze waveform viewers, check coverage metrics (code/functional), and debug RTL simulation failures.
- Automation & Scripting: Write and maintain automation scripts using Python , Perl , or Tcl to improve the efficiency of the verification flow.
- Documentation: Maintain clear documentation of test plans, coverage results, and bug reports.
Qualifications
- Third-year or Final-year student currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science or a closely related field (Physics, Maths).
- Be able to work onsite for 4 days per week.
- Be able to commit to at least a 6-month internship program.
- Strong verbal and written communication skills in English. Technical Skills: Strong foundational knowledge of digital logic design and Verilog/SystemVerilog .
- Familiarity with Object-Oriented Programming (OOP) and languages like C/C++ or Python .
- Basic understanding of UVM concepts, SVA (SystemVerilog Assertions), and IC design flows is highly preferred. Soft Skills: Strong analytical and problem-solving skills, paired with a collaborative team spirit and a passion for continuous learning .
- Benefit Package of Interns at Intel Vietnam Attractive internship allowance Training programs, opportunities to be involved in multinational projects.
- Exciting extracurricular and sports programs for employees Well-invested facilities, putting safety first.
- Shuttle bus system at many places in Ho Chi Minh City, Binh Duong, Dong Nai.
- High-quality cafeteria, lunch allowance.
- Safe, stable and dynamic working environment.
Sourced directly from Intel’s career page
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Salary range
₹5-12 LPA to ₹40-70 LPA
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Job ID
/job/Vietnam-Ho_Chi_Minh_City/Design-Verification-Intern_JR0285979
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