DDR PHY Firmware Engineer

About This Role

• Intel's Central Engineering Group is seeking a DDR/LPDDR Memory Subsystem Firmware Developer to design, develop, and validate DDR and LPDDR memory reference code for our next-generation products working at the critical hardware-software boundary, writing foundational initialization and training algorithms to ensure maximum bandwidth, strict power efficiency, and optimal signal integrity.
• In this role, you will drive solutions that seamlessly incorporate Intel's cutting-edge products and technologies, playing a pivotal role in enabling ecosystem and industry partners for platform readiness.
• You will have the opportunity to design, develop, and validate innovative solutions that shape the future of technology.
• By collaborating with internal and external teams, you will ensure Intel's products are market-ready and deliver exceptional performance, creating meaningful impact across industries.
• This role provides a unique opportunity to influence design, optimize customer experiences, and support the delivery of products that define Intel's success in a rapidly evolving market.
• Responsibilities will include but are not limited to: DDR/LPDDR Reference Code Development: write, maintain, support, optimize and debug low-level firmware in C and C++ for memory initialization, configuration, and runtime management.
• Implement and support advanced DRAM training algorithms (e.g., write/read leveling, VREF training) adhering to JEDEC specifications Execute and test firmware on architectural models, test chip platforms, simulation platforms (FPGA/emulation), and RTL environments before physical silicon is available.
• Participate directly in post-silicon bring-up in the lab, diagnosing and resolving complex hardware/firmware integration bugs.
• Partner with SoC architecture, analog design, and validation teams to ensure hardware features map correctly to software controls.
• Works closely with both the DDR/LPDDR PHY IP Design Team as well as the post silicon Electrical and Functional Validation teams.
• Document Memory Reference Code specifications and user guides for OEMs and internal platform engineering teams.
• Hands-on automation script development and optimization (using C/C++, Python).
• Well versed in the usage of advanced lab equipment.
• Publishes MRC validation plan and reports summarizing all validation activities performed, reviews results, and communicates to relevant teams.
• Collaborate with internal and external silicon, hardware, and software teams to deliver innovative market-ready solutions.
• Partner with customers' R and D and manufacturing teams to address factory challenges, integrate DFx requirements, and ensure smooth product ramp.
• Deliver product training and provide technical support to drive systematic improvements.
• Works validation engineers (e.g., platform, SoC, and sys debug) to understand bug escapes, debug MRC/IP related failures found in other environments Troubleshoot and resolve technical issues during development, testing, and production phases.
• Great team player, highly motivated to support the team with technical expertise and hands on experience in memory reference development and debug.
• Knowledge of High-Speed Oscilloscopes, Logic Analyzers, Data Acquisition Tools/Hardware.
• Collaborate with internal and external silicon, hardware, and software teams to deliver innovative market-ready solutions.
• Partner with customers' R and D and manufacturing teams to address factory challenges, integrate DFx requirements, and ensure smooth product ramp.
• Deliver product training and provide technical support to drive systematic improvements.
• The ideal candidate should show the following behavioral traits: Excellent communication and leadership skills.
• Proven analytical and problem-solving skills.