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About This Role
- Defines the physical dimensions of the CPU IP with consideration for overall product costs such as die size optimization, die per reticle/good die per wafer maximization, and right technology selection as it pertains to metal layers and reuse strategy across different SKUs in a product family.
- Performs integration of all dies in a package and completes the relevant checks before tapeout.
- Creates and physical database for the IP.
- Collaborates with architects to optimize the placement of IPs for latency as well as die area/aspectratio.
- Creates specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies.
- Collaborates with the clock design and logic design teams to deliver the physical block level floorplans for APR.
- Collaborates with the power delivery team on tradeoffs for metal allocation for signal and power.
Qualifications
- Job Requirement: In this role you will be responsible for all the aspects of Floorplan and pin placement activities.
- You will engage with Architecture, DFT and package to arrive at optimal chip planning early in the design cycle.
- You will work closely with physical design cluster leads to comprehend design challenges and arrive at optimal floorplan.
- You will play critical role in die size estimation and in evaluating Floorplan tools, methods and flows.
- Planning boundaries and pin densities to facilitate high confidence timing closure and routability.
- With your broad understanding of physical design you will play a critical role in identifying and solving multitude design issues at partition/cluster and full chip.
- Expertise with multiple aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I-O planning and hard IP integration.
Key Skills
- Experience with SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and advanced package technologies.
- Hierarchical design approach, top-down design, budgeting, timing and physical convergence.
- From a CAD tool perspective, experience with Floor planning tools, P and R flows, Physical Design Verification Flows is required.
- Familiar with various process related design issues including Design for Yield and Manufacturability.
Tools & Skills
EDA Tools
Sourced directly from Intel’s career page
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Specialisation
Salary range
₹5-11 LPA to ₹38-65 LPA
Open roles at Intel
627 positions
Job ID
/job/India-Bangalore/CPU-Floorplan-Lead_JR0286570
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