Chassis IP Senior Design Engineer

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Intel is seeking an experienced Logic Design engineer for the Intel Chassis Group, which is chartered to deliver the chassis for SoCs within Intel.
The role involves logic design of component and foundation IPs which can be used to build an SoC chassis.
The ideal candidate will have strong design and Verilog skills and some background in protocol conversion bridges for AMBA/CXL protocols.
Understanding of concepts such as QoS, access control, flow control, debug, RAS, security and error handling is a plus.
Key Responsibilities - Develop logic designs, register transfer level (RTL) coding, and simulations required for functional units, IP blocks, and subsystems. - Define and implement architecture and microarchitecture features for the interconnect IP block and sub-system which includes high-performance data plane and control plane routers, switches, arbiters, protocol conversion bridges, debug/trace components, and clock and power controls. - Perform rigorous quality checks and optimization of RTL designs to improve IP power, performance, area, and timing, ensuring delivery of high-quality IP. - Evaluate design trade-offs across area, bandwidth, timing, and reliability to achieve balanced and efficient IP functionality. - Support Sub-system/SoC customers with high-quality IP integration and verification workflows.

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with a minimum of 7 years of experience in logic design and RTL development. • Proficiency in hardware description languages, including Verilog and SystemVerilog. • Strong knowledge of digital design principles, such as timing analysis, power optimization, and area trade-offs. • Experience with industry-standard EDA tools for design, Quality checks and simulation (e.g., Synopsys, Cadence, Mentor Graphics).
Preferred Qualifications • Familiarity with AMBA (CHI, AXI, AHB, APB) and PCIe/CXL protocols is a plus • Experience in working with architecture, verification, SoC integration teams • Good understanding of PPA trade-offs • Ability to work with physical design to solve timing issues • Experience with use of AI to assist logic design is a plus In addition to the qualifications a successful candidate will demonstrate: • Communication skills • Capacity to work across large, geographically distributed engineering teams across multiple time zones.

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