Chassis IP Design Engineer

About This Role

• The Role and Impact As an IP Logic Design Engineer, you will be instrumental in developing and optimizing logic designs for high-performance IP blocks that drive Intel's cutting-edge SoC solutions.
• Your day-to-day responsibilities will include writing register transfer level (RTL) code, conducting simulations, and ensuring designs meet stringent power, performance, area, and timing goals.
• You'll play a pivotal role in delivering quality IPs while collaborating across architecture, verification, and SoC integration teams to ensure seamless handoffs and impactful results.
• Business group The Central Engineering Group (CEG) is Intel's leading innovation hub, focused on designing foundational technologies for integration across Intel's product portfolio.
• Within this team, the UIC Fabric Design organization specializes in developing reusable IP blocks and subsystems that enhance system-level capabilities.
• This group contributes to Intel's broader mission of delivering world-class solutions to revolutionize computing across industries.
• Key Responsibilities - Design and develop RTL code for IP blocks, ensuring functionality, quality, and scalability. - Optimize logic designs to meet power, performance, area, and timing objectives. - Collaborate with architecture teams to define microarchitecture features of IP designs. - Participate in verification plan reviews and implement corrective measures for failing RTL tests. - Support SoC integration teams to ensure high-quality integration and verification of IP blocks. - Work with physical design teams to address timing and implementation challenges. - Drive compliance with quality assurance standards for seamless IP-SoC handoff.