Analog Circuit Design Engineer

About This Role

• The Role and Impact: Join Intel's cutting-edge team as an Analog Circuit Design Engineer, where you will play a pivotal role in advancing analog and mixed-signal designs for high-speed interconnect solutions.
• You will design and verify analog circuits in advanced process nodes, contributing directly to Intel's next-generation innovations.
• Collaborating with cross-functional teams, you will optimize circuits for power, performance, area, timing, and yield goals while driving impactful solutions that shape Intel's leadership in technology.
• This role offers the opportunity to engage with some of the most innovative teams, pushing the boundaries of analog design and fostering technical excellence.
• Key Responsibilities: Design and optimize highspeed SerDes PHY analog blocks for 224G/112G SerDes.
• Should have silicon proven hands-on design experience in couple these blocks i.e.
• Clock and Data Recovery circuits, Phase Interpolators, DLL, Highspeed TX drivers and RX frontends circuits.
• Architect lowjitter, lowpower, and highlinearity circuits meeting stringent BER and jitter specifications.
• Perform transistorlevel design, simulation, and optimization for PVT corners, aging, mismatch, and reliability.
• Work closely with SerDes architects to translate systemlevel requirements (channel loss, BER, jitter tolerance, power, latency) into circuitlevel specifications.
• Support linklevel modeling and behavioral abstraction of analog blocks for toplevel system simulations.
• Contribute to architecture tradeoffs between performance, power, area, and testability.
• Drive presilicon verification using Spectre/HSPICE, AMS simulations, and MATLAB/Python modeling.
• Define and execute postsilicon validation plans, including debug, characterization, and bringup in the lab.
• Analyze silicon data and correlate with simulations; propose and implement ECOs as needed.
• Support compliance testing with standards such as IEEE 802.3 (112G/224G) and industry interoperability requirements.
• Interface with digital, firmware, packaging, SI/PI, and test engineering teams.
• Participate in design reviews, risk assessments, and schedule planning.