Sr Engineer Design Enablmt PDK

Nice to Have

• Experience in semiconductor and/or EDA industries with a focus on physical verification or DRC QA Good knowledge of electronic devices, semiconductor theory, and layout-dependent effects Experience working with DRC rule decks, including validation and regression testing Experience developing or extending DRC QA test cases and regression flows Experience with CAD systems in Electronics (Cadence IC / Virtuoso Layout, Cadence OrCAD, Protel or similar) Experience with scripting languages (Perl, Tcl, Bash, Python or similar) is a plus Exposure to Cadence IC (Virtuoso Layout, Schematic or Skill programming language) is a plus Previous experience with Unix/Linux systems is also a plus We Offer Attractive compensation package with competitive salary, performance related bonus plan and a global recognition program.
• Employee Stock Purchase Plan (including 20% match and 50 seed shares for first time participants, non-executive).
• Individual, technical or management career path opportunities supported by enhanced learning and development programs.
• We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard.
• Information about our benefits you can find here: https://gf.com/careers/opportunities-in-europe/