Senior Principal Engineer, SoC Design Verification

Nice to Have

• Experience with power-aware verification using UPF, including isolation, retention, and power-state transitions.
• Experience with a CPU architecture such as RISC-V, Arm, or MIPS.
• Experience with common SoC protocols or interfaces such as AXI, AHB, APB, SPI, I²C, or UART.
• Experience with UVM RAL, SystemRDL, IP-XACT, or register-model generation flows.
• Experience with formal verification, gate-level simulation, emulation, FPGA prototyping, or hardware/software co-verification.
• C or C++ experience related to embedded software, test development, or reference models.
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