Senior Engineer, ASIC Digital Design (System IP Verification)

Nice to Have

• Thesis, research, internship or project experience involving computer or processor architecture, RISC-V, cache or memory systems, interconnect/NoC, SoC integration, FPGA or digital verification.
• Exposure to SystemVerilog/UVM, constrained-random verification, assertions/SVA, functional or code coverage, formal verification, performance modeling or processor/subsystem-level validation.
• Familiarity with Linux, Git and EDA simulation or debug tools such as VCS / Verdi, Xcelium/SimVision, Questa, Verilator or equivalent tools.
• Experience applying Python, C/C++ or shell scripting to verification automation, test Interest in developing deeper expertise in cache coherency, memory ordering, interconnect protocols, low-power verification, functional safety/security or verification automation.
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