Master Thesis Student – Compiler Optimization for RISC-V Processors

Nice to Have

• Experience with LLVM or other compiler infrastructures.
• Knowledge of RISC-V architecture and instruction set concepts.
• Understanding of processor microarchitecture, pipelining, and performance optimization.
• Experience with benchmarking, profiling, or performance analysis tools.
• Exposure to embedded systems or low-level software development.
• What You Will Gain Practical experience with state-of-the-art RISC-V processor technologies.
• Hands-on involvement in LLVM compiler development and optimization.
• Exposure to real-world hardware-software co-design challenges.
• Mentorship from experienced processor and compiler engineers.
• An opportunity to contribute to cutting-edge research and development in processor performance optimization.
• If you are passionate about computer architecture, compiler technology, and performance engineering, we look forward to supporting your thesis journey in Leuven.
• Information about our benefits you can find here: https://gf.com/careers/opportunities-in-europe/