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What You'll Do
- Define and implement DFT architecture including Scan, MBIST, and Test Access Mechanisms .
- Lead Scan Insertion , ATPG Pattern Generation Develop and integrate MBIST solutions for embedded memories (SRAM/MRAM/ROM).
- Perform RTL-level DFT verification and debug.
- Execute and debug Gate-Level Simulations (GLS) with SDF back-annotation.
- Validate Scan Patterns, MBIST controllers, and test protocols across multiple modes (functional/scan/mbist test).
- Redundancy analysis (RA) flows Fuse/OTP programming for repair implementation Integration of repair signatures into test and bring-up flows Drive ATPG pattern generation, validation, and coverage improvement.
- Analyze failure logs and debug issues during simulation and silicon bring-up.
- Collaborate closely with Physical Design (PnR) teams for: Scan chain stitching and reordering.
- Write SDC for timing closure for test paths.
- Understand physical impacts of DFT (congestion, timing, power).
- Support silicon bring-up, ATE debugging, and manufacturing test strategies.
- Required Qualifications : BSEE/MSEE in Electrical Engineering with 10+ years of strong hands‑on experience in JTAG, Scan, Memory BIST, and ATPG Proficient in SystemVerilog and UVM‑based verification environments.
- Expertise with ATPG and MBIST tools, particularly Tessent (mandatory).
- Strong proficiency in testbench development, simulation, and debug.
- Experience in post‑silicon failure analysis, diagnostics, and debug.
- Ability to work with ATE patterns and perform gate‑level simulations.
- Skilled in scripting and automation using Tcl, Python, and Shell.
- Experience in RTL development and functional verification of logic circuits is an added advantage.
Nice to Have
- Experience in RTL development and functional verification of logic circuits.
- Strong communication skills and ability to work in cross-functional teams.
- We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.
- As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.
- All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.
- Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia
Sourced directly from GlobalFoundries’s career page
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Specialisation
Salary range
₹5-10 LPA to ₹35-58 LPA
Open roles at GlobalFoundries
673 positions
Job ID
/job/IND---Karnataka---Bengaluru---North/Lead-DFT-Engineer---MBIST_JR-2602961
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