Junior Design Layout Engineer

What You'll Do

• Join our high‑performance Physical Design Team, developing next‑generation ultra‑high‑speed circuits for Optical Engines.
• The layout team is handling multiple projects focused on the most advanced SOI and FinFET technologies, and beyond.
• Our team members are working on state-of-the-art, ultra-high-speed circuits, while pushing the limits in every aspect of speed, performance, and area.
• Physical implementation of Analog and Mixed-Signal circuits.
• Understanding complex constraints for advanced technologies.
• Floor planning, power planning, placement, and custom routing of ultra-high-speed sensitive blocks and signals.
• Advanced design flows and checks to fix IR, EM, and crosstalk issues.
• Address ESD and Latchup constraints and requirements.
• Block-level and top-level integration efforts.
• Co-Work with the front-end team to optimize the physical designs.
• Contribute to design reviews, documentation, and methodology improvements.
• Required Qualifications : Minimum 7 Years of related work experience.
• Proven track record delivering AMS blocks for production silicon.
• Strong industrial experience in analog/mixed‑signal CMOS layout.
• Experience in layout design of various circuit types such as TX, DRVRs, RX, TIAs, and PLLs.
• Experience with Chip releases and top-level ownership and deliverables.
• Experience with SOI or FinFET process technologies and BICMOS is a plus.
• Knowledge in scripting languages such as TCL, SKILL, PERL, and SVRF is a plus.
• We Offer Base Salary Equity Annual Bonus Plan Medical Insurance Information about our benefits you can find here: https://gf.com/careers/opportunities-in-europe/