DFT Engineer ( Testchip Architecture/ RTL DFT)
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What You'll Do
- Lead the DFT architecture for test‑chip designs.
- Develop and maintain DFT methodologies for the team.
- Possess strong knowledge of MBIST, at‑speed testing, test‑clocking, and port‑mixing.
- Own and deliver test architectures including Scan, Mem‑BIST, ATPG, and provide post‑silicon support.
- Collaborate effectively with cross‑functional design, verification, and physical design teams to ensure seamless BIST integration and validation Required Qualifications : BSEE/MSEE or PhD in Electrical Engineering with 7+ years of strong hands‑on experience in JTAG, Scan, Memory BIST, and ATPG Proficient in SystemVerilog and UVM‑based verification environments.
- Expertise with ATPG and MBIST tools, particularly Tessent (mandatory).
- Strong proficiency in testbench development, simulation, and debug.
- Experience in post‑silicon failure analysis, diagnostics, and debug.
- Ability to work with ATE patterns and perform gate‑level simulations.
- Skilled in scripting and automation using Tcl, Python, and Shell.
- Experience in RTL development and functional verification of logic circuits is an added advantage.
Nice to Have
- Experience in RTL development and functional verification of logic circuits.
- We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.
- As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.
- All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations." Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia
Tools & Skills
EDA Tools
Languages
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Salary range
₹5-12 LPA to ₹40-70 LPA
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64 positions
Job ID
/job/IND---Karnataka---Bengaluru---North/DFT-Staff-Engineer---Testchip-Architecture-_JR-2503220
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