CPU IP Design & Verification Engineer – RISC-V (2027 New College Graduate)
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What You'll Do
- Design and develop RISC-V CPU microarchitecture and SystemVerilog RTL design and development.
- Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts.
- Develop verification tests, assertions, checkers, and functional coverage for CPU features.
- Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms.
- Support functional and coverage closure through design and verification reviews.
- Support CPU power, performance, and area analysis and optimization.
- Develop Python, C/C++, or scripting-based automation to improve design, verification, regression, and debug productivity.
- Collaborate across architecture, design, verification, performance, and implementation teams to deliver high-quality CPU IP.
- Other Responsibilities: Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
- Required Qualifications: Education – Graduating with a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field from an accredited degree program.
- Must have at least an overall 3.0 GPA and proven good academic standing.
- Language Fluency - English (Written & Verbal) Strong foundation in digital logic design and computer architecture.
- Coursework, research, internship, or project experience with Verilog or SystemVerilog.
- Understanding of CPU fundamentals including pipelines, instruction execution, loads/stores, caches, and memory hierarchy.
- Programming or scripting experience with Python, C/C++, or similar languages.
- Strong analytical, problem-solving, and debugging skills.
Nice to Have
- Prior related internship or co-op experience.
- Demonstrated prior leadership experience in the workplace, school projects, competitions, etc.
- Project management skills, i.e. the ability to innovate and execute solutions that matter; the ability to navigate ambiguity.
- Strong written and verbal communication skills Strong planning & organizational skills Knowledge of the RISC-V Instruction Set Architecture (ISA).
- Experience with SystemVerilog/UVM, assertions, functional coverage, or constrained-random verification.
- CPU architecture, microarchitecture, FPGA, ASIC, or processor-design project experience.
- Familiarity with caches, memory subsystems, privilege modes, exceptions, interrupts, or virtual memory.
- Experience with simulation, waveform debug, Git, and Linux.
- Exposure to synthesis, lint, clock-domain crossing analysis, formal verification, or timing analysis.
- Assembly-language programming experience.
- Interest in using AI-assisted engineering tools to improve RTL design, verification, automation, and debug productivity. #NCGProgramUS Expected Salary Range $86,000.00 - $170,000.00 The exact Salary will be determined based on qualifications, experience and location.
- If you need a reasonable accommodation for any part of the employment process, please contact us by email at usaccommodations@gf.com and let us know the nature of your request and your contact information.
- Requests for accommodation will be considered on a case-by-case basis.
- Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.
- An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations.
- GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential.
- GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people.
- Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.
- All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law
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/job/USA---Texas---Austin/CPU-IP-Design---Verification-Engineer---RISC-V--2027-New-College-Graduate-_JR-2604136
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