Sr. Principal Product Engineer

Requirements

• Bachelor’s in Electrical / Electronics / VLSI Engineering with 10+ years of related experience, or MS with 8+ years, or PhD with 6+ years.
• Deep hands-on experience with industry-standard IR/EM (EMIR) and PDN analysis tools and digital physical implementation / signoff flows.
• Strong background in CMOS/digital design, power IR-drop analysis, circuit analysis, and low-power / multi-power-domain chip power-integrity signoff.
• Proven ability to separate critical issues from noise, debug large SoC/PDN problems, and close the loop from customer requirement to R&D fix to deployment.
• Scripting in Tcl and Python; strong written, verbal, and presentation skills with customer and executive audiences.
• Preferred Direct experience with Voltus and adjacent Cadence digital signoff/implementation tools (Integrity, Tempus, Innovus, Quantus/QRC). 3DIC / chiplet, electrothermal, and advanced FinFET or GAA node experience.
• Prior technical leadership of PE/AE teams or of a strategic account/foundry program.
• The annual salary range for California is $161,000 to $299,000.
• You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
• Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.
• Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
• Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
• We’re doing work that matters.
• Help us solve what others can’t.