Sr Principal Design Engineer

Nice to Have

• Experience with Cadence simulation and/or emulation products.
• Experience with hardware emulation, simulation, or other hardware-based verification platforms.
• Programming or scripting experience with Perl, Tcl/Tk, C-shell, or similar languages.
• Experience with memory subsystem architecture, design, and operation.
• Experience designing or verifying memory protocols such as LPDDR, HBM, NAND Flash, eMMC, SD, DFI, or UFS.
• Experience developing reusable IP models or verification components for complex SoC or system-level environments.
• What Success Looks Like Success in this role means delivering robust, reusable, and customer-ready memory IP models while continuously improving existing products.
• You will combine deep RTL and verification expertise with strong debugging, communication, planning, and collaboration skills to solve challenging problems and help advance the quality and capabilities of the overall memory IP portfolio.
• The annual salary range for California is $154,000 to $286,000.
• You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
• Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.
• Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
• Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
• We’re doing work that matters.
• Help us solve what others can’t.