Sr Principal Design Engineer (Chiplet Solutions)

What You'll Do

• Technical leadership of complex Silicon programs consisting of leading-edge IP Work closely with our Chiplet Architecture team to define next generation Chiplets Integration of Cadence IP Solutions e.g.
• UCIe, PCIe, Ethernet, USB, NPU, Audio, Vision Integration of partner IP Solutions e.g.
• CPUs, ISP, Silicon Monitors, NoCs Hands-on leadership of RTL, Testbench, Formal Analysis and Trial Synthesis activities Quality Assurance, via implementation of hierarchical LINT, CDC and release flows Planning of activities and milestones for Chiplet Subsystems and System IP development Leadership of cross-functional technical meetings with domain leads e.g.
• Verification, SW Support customer pre-sales and post-sales meetings Participate in Technical Review Meetings and Checklist Reviews as part of ISO-9001 Represent Cadence by presenting at Industry Conferences such as IEEE, DAC, CDNLive Job Qualifications: Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline 12+ years’ experience in microelectronics/EDA industry Experience of Verilog RTL Design essential Experience of Metric Driven Verification (MDV) essential Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential Experience of SoC Architecture and Development essential Experience of Technical Team leadership essential Excellent oral and written English essential Self-motivated with excellent planning, interpersonal, and communication skills Additional Skills/Preferences: Experience of AMBA, PCIe, CXL & UCIe protocols preferred Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization.
• We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
• Travel: <10% We’re doing work that matters.
• Help us solve what others can’t.