Sr Principal Design Engineer

What You'll Do

• Architect and implement RTL for PCIe IP blocks Collaborate with system architects to define micro-architecture and design specifications.
• Responsible for the quality of Design Quality.
• Expertise in LINT/CDC, Synthesis is Must.
• Work closely with verification teams to develop testbenches and validate functionality.
• Participate in interoperability testing Contribute to performance, power, and area optimization in advanced nodes.
• Interface with cross-functional teams including PHY, software, and validation.
• Required Skills Strong hands-on experience in RTL design using Verilog/SystemVerilog.
• Deep understanding of PCIe protocol stack and transaction layers.
• Experience with AXI & PXC interfaces, DMA engines, and MSI interrupt handling, Familiarity with CDC design principles and asynchronous FIFO implementation.
• Proficiency in synthesis, linting, and static timing analysis.
• Exposure to formal verification and assertion-based design methodologies.
• Experience with simulation tools and waveform debugging.
• Education Bachelor’s or Master’s degree in Electronics /Electrical Engineering , or related field.
• We’re doing work that matters.
• Help us solve what others can’t.