Sr Application Engineer – SerDes Design IP

SAN JOSEAnalog/MSVery High demand

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About This Role

  • The Cadence IP team develops industry leading IPs that enable customers in a variety of markets - from the endpoint to the edge to the cloud.
  • At Cadence we’re helping set the standard on IP products that get integrated in SoCs that power the world’s Data Centers, Automobiles, Cloud and Wireless Systems.
  • We offer amazing opportunities to grow, no matter where you are in your career.
  • We are growing our Serdes Applications team and we are looking for smart, energetic, collaborative and creative people to help us lead the industry with our IP products.
  • At Cadence, we believe in embracing diverse ideas and striving for excellence in all that we do.
  • Do you want to make a difference and be challenged? Join the High-Performance Culture at Cadence.
  • As a Senior Applications Engineer, you will use your knowledge of different high-speed interface standards such as PCIe, CXL, Ethernet and USB to provide technical pre-sales support to win design IP business.
  • Showcase the performance of the IP through demos at industry events.
  • This role offers the benefit of both technical growth and business skill development.
  • You will be part of the Technical Field Organization helping educate customers and providing solutions to them using our Serdes IP portfolio.
  • As you grow into more senior roles, you will use your knowledge of different high-speed interface standards to architect solutions for customers using Cadence IPs.
  • Our serial interface PHY and controller IPs are used in data centers, mobile devices, automobiles and consumer devices.
  • Cadence offers great benefits and has a friendly hybrid work policy.

What You'll Do

  • Technical pre-sales of High-Speed Interface IP, including PCIe, CXL and Ethernet PHY and Controllers Present Cadence’s IP portfolio and capabilities to prospective customers Work closely with IP Sales staff, marketing and R&D teams to win opportunities Provide quick-turn product specific technical support to customers, field teams, architects and designers Write application notes and articles for internal and/or external publication Travel to customer sites may be required occasionally Qualifications: 2+ years of industry experience on high-speed interface controller and/or PHY design/verification 2+ years of industry experience on one or more high speed interface protocols – PCIe, CXL, UCIe, Ethernet, USB, MIPI, 112G, 56G Working knowledge of high-speed interface PHY Lab validation or demo setup experience BS in EE, CE or related equivalent with 2+ years of relevant work experience or MS in EE, CE or equivalent Individual leadership and initiative to manage pre-sales accounts Excellent presentation skills and verbal/written communication skills is a must The annual salary range for California is $102,900 to $191,100.
  • You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
  • Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.
  • Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
  • Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
  • We’re doing work that matters.
  • Help us solve what others can’t.

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Specialisation
Salary range
₹4-10 LPA to ₹40-75 LPA
Open roles at Cadence Design Systems
143 positions
Job ID
/job/SAN-JOSE/Lead-Applications-Engineer---DDR-Design-IP_R51279

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