Senior Principal Design Engineer

About This Role

• – Verification Engineer (PCIe Design IP) Experience: 7 to 15 Years We are hiring motivated and passionate Verification Engineers to join our PCIe Design IP group .
• Key Responsibilities Verify PCIe Design IP across multiple generations Develop and maintain SystemVerilog/UVM-based verification environments Collaborate closely with design, architecture, and validation teams Contribute to verification strategy, coverage closure, and sign-off activities Required Skills Strong hands-on experience with SystemVerilog and UVM Solid background in functional verification of PCIe Good understanding of verification methodologies and best practices We’re doing work that matters.
• Help us solve what others can’t.