Opens cadence.wd1.myworkdayjobs.com in a new tab
Overview
- At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- We are looking for an experienced C++ software engineer to join the Protium Software Development Team to develop and enhance the FPGA-Based Prototyping product which is used by leading CPU/GPU/HyperScaler companies for pre-Silicon software validation of their SOC’s.
- You will develop new algorithms and optimizations for QoR (Quality of Results) and performance for the Protium Timing flow working with a small team of engineers to develop our next generation FPGA based verification platform.
What You'll Do
- Enhance and support Timing Engine to add new features and extend existing features Enhance and support Timing Flow to improve P&R compile time The role involves designing, tuning, and innovating timing graph algorithms and flow operating on multi‑billion‑node timing graphs Write Specifications and Unit Tests for your code Position Requirements/Qualifications: BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience Experience in EDA software development.
- Strong background in SDC constraints and Timing Analysis Excellent programming skills in C/C++ Strong knowledge of Tcl is preferred Experience in multi-threaded/ concurrent programming are pluses.
- Prior experience with Emulation or FPGA software development is an added plus.
- The annual salary range for California is $154,000 to $286,000.
- You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
- Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.
- Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
- Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
- We’re doing work that matters.
- Help us solve what others can’t.
Sourced directly from Cadence Design Systems’s career page
Your application goes straight to Cadence Design Systems.
Opens cadence.wd1.myworkdayjobs.com in a new tab
Specialisation
Open roles at Cadence Design Systems
144 positions
Job ID
/job/SAN-JOSE/Senior-Principal-C---Software-Engineer_R54404
Get matched to roles like this
Upload your resume once. We’ll notify you when matching roles open up.
Join talent pool — freeSimilar Other roles
Samsung Semiconductor
Senior Director, Architecture Research Lab
San Jose, California, United States|Other
Micron Technology
PRINCIPAL ENGINEER, SSD VALIDATION
MSB, Singapore|Other
Micron Technology
MGR, F16 HVM PROCESS WET/CMP
Taichung - Fab 16, Taiwan|Other
Micron Technology
Shift Engineer, MTB PWF WET
Taichung - MTB, Taiwan|Other