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What You'll Do
- Develop cycle-level performance models in SystemC or C++ Correlate performance models to match RTL configurations and traffic conditions Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc) Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks Required Skills BE/B.Tech ME/M.Tech in ECE, E&TC, CS or similar 5+ years of experience in hardware modeling, functional or performance Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM) Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs We’re doing work that matters.
- Help us solve what others can’t.
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Specialisation
Open roles at Cadence Design Systems
145 positions
Job ID
/job/NOIDA/Principal-Software-Engineer_R48605-1
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