Principal Software Engineer

What You'll Do

• This role will be with the Quantus product.
• Quantus is the industry leading parasitic extraction software product that enables cutting edge chip design across the globe.
• R&D Software Engineering role in Parasitic Extraction area is a multi-faceted position encapsulating a mix of software development, algorithm development, software debugging, performance optimization, accuracy analysis, GUI development and integration with layout/schematic editors as well as state of the art simulators.
• You will be also expected to design, develop, fix bugs and respond to customer queries, define project completion checklists; collaborate with cross-function teams.
• You will have a chance to contribute to the main Physical Verification flows in EDA industry and your work will be visible through billions of electronic devices deployed worldwide.
• Job Qualifications: Bachelor’s in computer Science or Electrical Engineering; + 7 years of related experience or Masters + 5 years related experience Key Skills Hands-on coding & debugging (C++) in a UNIX environment for computationally intensive applications.
• Experience of working with multiple developers on large codebases is valued Proven ability to make programs run faster and consume less memory using algorithmic optimization, multi-threading, distribution, HPC.
• Ability to analyse complexity (big O notation) is a must Familiar with the full software development lifecycle from Requirements to final delivery.
• Software development environments, version control, Linux, scripting languages such as Tcl/Perl/Python Excellent communication skills - the ability to share complex ideas & information is paramount .
• Additional Skills/Preferences: Existing EDA tool development experience Maths or physics background with knowledge and implementation experience of any of the following: Computational geometry, numerical methods, solving large systems of linear equations, Maxwell’s equations & model order reduction GUI development, ideally using QT Knowledge and implementation experience with the chip design flow, layout connectivity, parasitic extraction, LEF/DEF is a big plus We’re doing work that matters.
• Help us solve what others can’t.