Principal Product Validation Engineer

What You'll Do

• Will work on complex problems that require innovative thinking, debugging customer reported problems and collaboration with R&D to propose out-of-box solutions with emphasis on robustness, PPA and scalability.
• Role Responsibility Work as a DFT Product Validation Engineer on insertion and validation of DFT technologies such as 1500 Wrapper, Boundary Scan, Compression, RTL DFT, Hierarchical Test, LBIST etc. using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on in-house and customer designs.
• Create testplans for verification of new features and execute them by creating new test cases requiring application of Design & DFT skills; Report bugs/enhancements in tool.
• Collaborate with R&D and Product Engineering teams to review feature specifications, testplans & customer issues.
• Debug issues reported by customers and suggest/implement measures to plug the gaps.
• Position Requirements Candidate is expected to be: B.E. in Electronics/Electrical Strong in Digital electronics, Verilog Good understanding of DFT techniques and methodologies Familiarity with Test standards like 1149.1, 1500, 1687 is a plus Experience with Cadence Test or other Test tools is preferred Good scripting skills (Tcl, Perl) Strong analysis and problem solving skills Good communication skills are a must Keen & quick learner ready to learn new things with little guidance & take up challenging tasks Education: B.
• This position is in Product Validation Team of Cadence Modus DFT Software Solution .
• Modus is a DFT (Design for Testability) software tool from Cadence used by leading chip design companies during DFT synthesis & ATPG (Automatic Test Pattern Generation) phase of chip design process.
• We’re doing work that matters.
• Help us solve what others can’t.