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What You'll Do
- Responsible for supporting integration / customization / post silicon bring up of CDNS DDR IP subsystems.
- Analyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers.
- Support DDR Controller and PHY SOC integration reviews, and integration questions.
- Perform RTL and gate level simulations to verify functionality.
- Assist customers with gate level simulations and timing closure.
- Participate in development of CDNS documentations and checklists for customers.
- Support post silicon bring-up and deployment activities by our customers.
- Enhance customer experience by providing prompt updates to customers.
- We’re doing work that matters.
- Help us solve what others can’t.
Tools & Skills
EDA Tools
Sourced directly from Cadence Design Systems’s career page
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Specialisation
Open roles at Cadence Design Systems
145 positions
Job ID
/job/BANGALORE/Principal-Design-Engineer_R45744-1
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