Principal Design Engineer

Overview

• At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
• Candidate should have worked on Finfet technology layouts.
• Exposure to technology nodes like 3nm/5nm and 7nm is required.
• Candidate should have 6+ years of experience in custom layout.
• Experience on high-speed analog mixed-signal layout is desirable.
• Role: Candidate will own and Lead Major blocks of Memory PHY Layout design.
• Candidate would perform hand-on design of critical analog and high-speed layout blocks.
• Candidate would co-ordinate design work with Circuit leads, layout contractors and layout team members.
• Candidate would participate in layout reviews by presenting and reviewing custom layout designs.
• We’re doing work that matters.
• Help us solve what others can’t.