Principal Design Engineer

What You'll Do

• Architect solutions for the latest DDR controller features and customer requirements.
• Design RTL in a highly configurable and automated environment.
• Work in small project teams.
• Work across disciplines with Design Verification, Support, Delivery, Application Engineers, PHY design team, etc.
• Utilize Cadence’s Design Automation flow and IP development tools.
• Develop high speed circuits and low power features.
• Improve quality and efficiency and help refine development process for greater productivity of the team through automation and improved methods.
• Participate in an engineering team to advance our product.
• Job Qualifications: Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline. 10+ years’ experience in microelectronics/EDA industry.
• Experience of Verilog RTL Design essential.
• Experience of Metric Driven Verification (MDV) essential.
• Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential.
• Experience of SoC Architecture and Development essential.
• Experience of Technical Team leadership essential.
• Excellent oral and written English essential.
• Self-motivated with excellent planning, interpersonal, and communication skills.
• Additional Skills/ Preferences: Experience of AMBA protocols such as CHI, AXI, AHB & APB preferred.
• Experience of SystemVerilog for design preferred.
• Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred.
• Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization.
• We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
• We’re doing work that matters.
• Help us solve what others can’t.