Physical Design Engineer (PNR/Physical Verification/STA/EMIR)
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What You'll Do
- Participating in or leading next-generation physical design, methodology, and flow development in advanced technology nodes. -Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
- Position Requirements: - Bachelor or above degree in majors of EE/CS/IT, with 5+ years work experience - Extensive knowledge of the design rule for the process of N7/N5 and below - Knowledge of scripting languages and use in methodology - Ability of fixing the physical design violations, including: DRC, DFM, LVS, ANT, ERC etc. - Deep experience of static timing analysis - Ability to learn quickly - High level of communication and teamwork - Carefulness, responsibility, and persistence We’re doing work that matters.
- Help us solve what others can’t.
- We welcome applications from candidates with disabilities and in equity seeking groups.
- If you have accessibility needs during the application and interview process, we encourage you to make your needs known.
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Specialisation
Salary range
₹5-11 LPA to ₹38-65 LPA
Open roles at Cadence Design Systems
630 positions
Job ID
/job/MOUNT-ROYAL-Montreal/Physical-Design-Engineer--PNR-Physical-Verification-STA-EMIR-_R53457
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