Opens cadence.wd1.myworkdayjobs.com in a new tab
Nice to Have
- Experience with a commercial or open-source FEA code (Abaqus, ANSYS, LS-DYNA, COMSOL, Code_Aster, FEniCS, deal.II, MOOSE) — as a developer, not only a user. - Nonlinear FEA: large deformation, contact, plasticity, creep, or viscoplasticity. - Parallel programming: OpenMP, MPI, or multithreaded C++. - Direct and iterative sparse solvers (MUMPS, PARDISO, SuperLU, hypre/BoomerAMG, PETSc) and graph partitioning (METIS/ParMETIS). - Mesh generation, mesh quality metrics, or computational geometry. - Semiconductor packaging or PCB background: 3D-IC, HBM stacks, solder reliability, warpage. - Development on Windows, and on Linux; Git or Perforce.
- We’re doing work that matters.
- Help us solve what others can’t.
Tools & Skills
Languages
Sourced directly from Cadence Design Systems’s career page
Your application goes straight to Cadence Design Systems.
Opens cadence.wd1.myworkdayjobs.com in a new tab
Specialisation
Open roles at Cadence Design Systems
597 positions
Job ID
/job/SHANGHAI/Lead-Software-Engineer_R55918
Get matched to roles like this
Upload your resume once. We’ll notify you when matching roles open up.
Join talent pool — freeSimilar Other roles
Samsung Semiconductor
Technical Director, Large-Scale AI Model Inferencing
San Jose, California, United States|Other
Samsung Semiconductor
Technical Account Manager, DRAM Business Enablement
San Jose, California, United States|Other
Samsung Semiconductor
Staff Engineer, Storage Product Planning
San Jose, California, United States|Other
Samsung Semiconductor
Staff Engineer, Storage Business Enablement
San Jose, California, United States|Other