Lead Product Validation Engineer

What You'll Do

• & Skills: (Design Verification Engineer) The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL).
• Prior experience in simulation/emulation using these languages.
• He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools.
• Experience in process automation with scripting.
• Experience with SystemVerilog, C++, UVM.
• Experience with Functional Verification of complex digital systems, e.g.
• SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog.
• Experience designing and implementing complex functional verification environments is required.
• Knowledge of protocols like PCIe, USB3/4, DP an added advantage.
• Qualifications Minimal qualification requires B.
• Tech/B.E./M.E. with 3-6 years of experience in relevant experience.
• Behavioral skills required.
• Must possess strong written, verbal and presentation skills.
• Ability to establish a close working relationship with both customer peers and management.
• Explore what’s possible to get the job done, including creative use of unconventional solutions.
• Work effectively across functions and geographies.
• Push to raise the bar while always operating with integrity.
• We’re doing work that matters.
• Help us solve what others can’t.