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What You'll Do
- / Skills · Full-chip and block-level implementation from RTL to Signoff, including place-and-route, timing closure, physical verification, power analysis, and optimization.
- Strong understanding of physical design fundamentals including floorplanning, placement, clock tree synthesis, routing, timing analysis, signal integrity, IR drop, and electromigration.
- Experience with timing closure methodologies for setup, hold, power, and area optimization.
- Familiarity with low-power implementation techniques including UPF/CPF, power gating, multi-voltage designs, clock gating, and leakage optimization.
- Need to be automation savvy and able to develop scripts, utilities, and methodologies to improve productivity and design quality.
- Prior experience in Python, Tcl, Perl, Shell, or other programming/scripting languages is a plus.
- Exposure to machine learning and AI-assisted optimization techniques is a plus.
- Familiarity with industry-standard implementation and signoff tools Understanding of advanced technology nodes (5nm and below) and associated challenges including congestion, variability, power integrity, and manufacturability is desirable.
- Strong debugging and problem-solving skills with the ability to analyze complex design issues and drive them to resolution.
- Good communication skills and ability to work effectively with cross-functional teams including architecture, RTL, verification, methodology, and CAD teams.
- Experience with data analytics, design-space exploration, or AI-driven optimization frameworks for improving PPA and productivity is highly desirable.
- Experience in PPA optimization, design convergence, benchmarking, methodology development, and large-scale CPU/GPU implementation is a plus.
- The annual salary range for California is $119,000 to $221,000.
- You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
- Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.
- Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
- Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
- We’re doing work that matters.
- Help us solve what others can’t.
Sourced directly from Cadence Design Systems’s career page
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Specialisation
Open roles at Cadence Design Systems
674 positions
Job ID
/job/SAN-JOSE/Lead-Product-Engineer_R56957
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