Lead Product Engineer - Design Verification (MM/VIP)

What You'll Do

• Leads projects with high resource, risk and/or complexity Develops and leads large and multiple cross-functional and cross-organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity Continually evaluates technology effectiveness/data interoperability of complex systems Manages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products Communicates highly complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view.
• Experience and Technical Skills required At least 4 – 8 years of experience with Design and Verification Experience with Developing Verification environments using SystemVerilog Working knowledge and experience with the UVM methodology Good experience on solving complex problems where analysis of situations or data requires an in-depth evaluation of various factors.
• Exercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results.
• Excellent problem-solving and debugging skills Familiarity with Memory protocols is a must.
• Knowledge of the DFI protocol is a plus.
• Qualifications BTech/BE/MTech/ME or equivalent with Electrical, Electronics & Comm or Computer Science Engineering Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters.
• Help us solve what others can’t.