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What You'll Do
- Develop and support adoption of generative AI tools to create and update, UVM and Formal verification environments Develop methodology guidance and end to end flows to ensure AI tools used in a consistent, efficient and predictable way Develop and roll out solutions that reduce verification debug time Automate documentation checking to improve quality and consistency Build tools and processes to support verification planning Optimise UVM regressions through improved automation and machine learning Maintain and develop best practices for Functional Safety Verification, Gate Level Simulation and Low Power Verification Maintain and improve design review checklists and quality documentation Job qualifications and required skills: Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline 4+ years experience in the microelectronics/EDA industry Proficiency in SystemVerilog and assertions Hands-on experience with Metric Driven Verification (MDV) Strong knowledge of constrained-random verification techniques (e.g.
- UVM) Excellent spoken and written English Self-motivated, with strong planning, interpersonal, and communication skills Additional Skills/Preferences: Formal verification experience and related applications Proficiency with scripting languages (e.g.
- Python) Knowledge of AI agent development (tools, concepts, and infrastructure) Methodology development and change management experience Familiarity with front-end design tools (e.g.
- LINT, CDC analysis) Exposure to quality processes and standards (e.g.
- ISO 9001, ISO 26262) Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization.
- We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
- Check what we can offer you: Competitive salary 25 days holiday per year Private Medical and Dental plans, Income Protection and Life Insurance Group Personal Pension Plan Cycle to work scheme and gym subsidy 5 days paid time to volunteer to give back to our communities Employee Stock Purchase Plan The opportunity to work for a Great Place to Work© & Fortune 100 organization Travel: <5% We’re doing work that matters.
- Help us solve what others can’t.
Sourced directly from Cadence Design Systems’s career page
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Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
Open roles at Cadence Design Systems
658 positions
Job ID
/job/EDINBURGH-01/Lead-Digital-Verification-Engineer_R54228
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