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Nice to Have
- Experience developing or using AVIP (Accelerated VIP) solutions Experience with end-to-end system validation flows (simulation → emulation → prototyping) Knowledge of UVM and verification frameworks Knowledge of Qemu/Gem5 or other system emulation projects Experience with multi-language environments (SV + C/C++ + Python) Familiarity with Emulation/Prototyping flows Exposure to AI/ML techniques applied to verification or tooling Strong problem-solving skills and ability to work independently Soft Skills Excellent English communication skills (both verbal and written) are required.
- Strong learning capability and adaptability to new technologies Ability to collaborate across global teams Proactive mindset in problem solving and customer engagement We’re doing work that matters.
- Help us solve what others can’t.
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Specialisation
Open roles at Cadence Design Systems
591 positions
Job ID
/job/SHANGHAI/Lead-Design-Engineer-Virtual-Solution-_R54953
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