Lead Design Engineer ( Synthesis/LEC/CLP )

What You'll Do

• Run and debug LEC sign off on design blocks; investigate and resolve NEQs and constraint mismatches Work on Genus synthesis runs to improve QoR, debug SDC/constraint issues.
• Support CLP flows Write and maintain ECO scripts and timing/power constraints for design blocks Independently triage and document issues, escalating complex or systemic issues as needed.
• Collaborate with PD, DFT, and RTL teams to resolve cross-functional issues affecting synthesis/LEC/CLP closure Prepare clear status updates and technical summaries for internal tracking Required Skills 5–8 years of hands-on experience in ASIC synthesis, LEC, and/or low-power verification flows Working knowledge of Cadence Genus and Conformal (LEC and/or CLP) Familiarity with UPF/CPF-based power intent (IEEE 1801) Scripting proficiency in Tcl, Perl, or Python; comfortable in Unix/Linux based environments.
• Solid understanding of digital design fundamentals, STA basics, and low-power architecture concepts Strong communication skills and ability to work independently on assigned blocks Regards K Madhu Prasad kmadhup@cadence.com We’re doing work that matters.
• Help us solve what others can’t.